There's a further PIC specific fly in the ointment. If the firmware uses PGC and/or PGD as normally high outputs (or on 18 pin PICs, if T1OSC is enabled on those pins) and you disable /MCLR reset, and there is a clock source (internal or external), and the board is externally powered or has a battery, you wont be able to reprogram the PIC as ICSP mode entry requires /MCLR to rise to Vpp while PGC and PGD are held low, but if power is applied before the rising edge of /MCLR the firmware runs and sets conflicting levels on the I/O pins preventing correct ICSP mode entry.
There was also a bug on really old PICs (about 25 years ago) that could result in 'off by N' addressing during ICSP. The same hardware was used for the program counter and ICSP address counter, and if four external clock cycles occurred while /MCLR was rising, the counter would be incremented and start from address 0x001 instead of 0x000 as it was supposed to. If /MCLR was pathologically slow rising and you had a fast external clock, it could get incremented more than once. The solution was to ground OSC1 during programming.